The use of a single bit error correction, double bit error detection circuits based on modified Hamming codes is common in prior art fault tolerant memory and data transmission systems. In such prior art systems the correction circuit is part of the hard core of the system. Therefore, the correction circuit must be fault free.
It is the general object of the present invention to provide an improved error correction circuit which can correct single bit errors and detect double bit errors.
It is a further object of the present invention to provide an improved error correction circuit in which any single parity check subcircuit can fail without corrupting the information bits of a correct input data pattern.
It is an additional object of the present invention to provide an improved error correction circuit which will allow a using system to remain UP if there is a single bit error in the input data pattern or faults in a single parity check subcircuit.
It is still another object of the present invention to provide an improved error correction circuit which will respond to the occurrence of both a single bit error in the input data pattern and faults in a single parity check subcircuit by either reporting a double bit error or providing a correct output with no error indication.
These and other objects, features and advantages of the present invention will become more apparent from reading the Description of the Preferred Embodiment in conjunction with the drawings.